The present invention relates generally to a duty cycle discriminating circuit, and more particularly to a duty cycle discriminating circuit which is used, for example, in a video tape recorder and the like and in which a threshold point of duty cycle discrimination can be varied.
A duty cycle discriminating circuit or a pulse width discriminating circuit is used, for example, in a video tape recorder (VTR), such as a VHS type VTR, and the like. The duty cycle discriminating circuit is used for determining whether a duty cycle of an input pulse signal is larger or smaller than a threshold value.
As one of conventional duty cycle discriminating circuits, there is known a discriminating circuit used in a VISS detecting circuit which is integrated in xcexcPD78492x series IC devices manufactured by NEC Corporation.
The VISS is an abbreviation of VHS Index Search System and is used, for example, for detecting or indexing a start portion of a playback video signal. In the VISS detecting circuit, a duty cycle discriminating circuit is used to detect a predetermined binary pattern, that is, a VISS pattern corresponding an index signal. The predetermined binary pattern is represented by using binary xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d corresponding to different duty cycles of a control signal recorded, for example, on a VHS video tape.
FIG. 10 is a block diagram showing a conventional duty cycle discriminating circuit used in the VISS detecting circuit. FIG. 11 is a timing diagram showing an operation of the duty cycle discriminating circuit of FIG. 10. The duty cycle discriminating circuit of FIG. 10 comprises an up/down counter with sign bit or a signed up/down counter 51, a preset value register 52, an edge detecting circuit 55, a control register 56, and a latch circuit 58.
The up/down counter 51 receives a count clock signal FCLK having a fixed frequency. The up/down counter 51 also receives a playback control signal (PBCTL signal), and performs a count up operation or a count down operation depending on the potential level of the PBCTL signal. For example, when the PBCTL signal is xe2x80x9c0xe2x80x9d, the up/down counter 51 performs a count down operation, and when the PBCTL signal is xe2x80x9c1xe2x80x9d, the up/down counter 51 performs a count up operation. An enable/clear of the up/down counter 51 is controlled by a signal from the control register 56.
The preset value register 52 stores a data value to be written into the up/down counter 51. The data value is outputted from the preset value register 52 in synchronization with a falling edge of a re-load signal supplied from the edge detecting circuit 55.
The most significant bit (MSB) of the up/down counter 51 is a sign bit. When the sign bit is xe2x80x9c0xe2x80x9d, the up/down counter 51 shows a positive number, and when the sign bit is xe2x80x9c1xe2x80x9d, the up/down counter 51 shows a negative number. This most significant bit (MSB) is inputted to the latch circuit 58. The latch circuit 58 may be a D-type flip-flop circuit, and holds the MSB of the up/down counter 51 in response to a rising edge of the re-load signal outputted from the edge detecting circuit 55. The MSB held by the latch circuit 58 becomes an output signal, that is, a discrimination result signal, of the duty cycle discriminating circuit.
The edge detecting circuit 55 outputs a re-load signal when it detects an edge designated by the content of the control resistor 56.
It is possible to write data into the control register 56 and into the preset value register 52 from a central processing unit (CPU) and the like which is disposed outside of this pulse width discriminating circuit and which is not shown in the drawing.
With reference to FIGS. 11A-11C, an operation of the conventional duty cycle discriminating circuit of FIG. 10 will be described briefly. As shown in the timing diagrams of FIGS. 11A-11C, the conventional duty cycle discriminating circuit of FIG. 10 discriminates duty cycles by using the up/down counter 51 with a sign bit or a signed up/down counter 51. The up/down counter 51 counts up the count clock signal FCLK during a period in which the PBCTL signal is in a high potential level, and counts down the count clock signal FCLK during a period in which the PBCTL signal is in a low potential level.
Usually, in order to reduce an error of discrimination, when the duty cycle of the PBCTL signal is to be discriminated, a middle value between the possible duty cycles is previously stored in the preset value register 52.
That is, in the VISS detection, the PBCTL signal has a duty cycle of 60% and a duty cycle of 30% (correctly, 27.5%), corresponding, for example, to xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d for representing binary data. Therefore, discrimination between these two kinds of duty cycles is performed by using a duty cycle of approximately 45%, which is a middle value between 60% and 30%, as a threshold point.
In order for the up/down counter 51 to become zero after one period of the PBCTL signal when the PBCTL signal having a duty cycle of 45% is inputted into the up/down counter 51, it is necessary to store a count value corresponding to 10% of one period of the PBCTL signal into the preset value register 52. As an example, when one period of the PBCTL signal corresponds to 200 clock pulses, it is necessary to store data xe2x80x9c20xe2x80x9d into the present value register 52.
In this structure, when the duty cycle of the PBCTL signal is larger than 45%, for example, 60%, the count value of the up/down counter 51 with sign bit becomes a positive value, and when the duty cycle of the PBCTL signal is smaller than 45%, for example, 30%, the count value of the up/down counter 51 with sign bit becomes a negative value. Thereby, it is possible to discriminate the duty cycle of the PBCTL signal.
As a second prior art technology for duty cycle discrimination, the following method is known which is not shown in the drawing.
That is, in this method, a counter and two registers A and B are used. The counter receives and counts up a clock pulse signal having a constant period. The registers A and B store count values of the counter during particular times specified by a signal to be measured or discriminated. The register A stores a count value corresponding to a time during which the signal to be measured is in a high potential level, and the register B stores a count value corresponding to one period of the signal to be measured.
The duty cycle of the signal to be measured is obtained by performing an arithmetic operation on the values stored in the registers A and B by an external CPU.
That is, the duty cycle is obtained by the following arithmetic operation.
Duty cycle=(count value of register A)/(count value of register B)
This method is very simple, and provides a precise duty cycle value.
As a third prior art technology, there is known a duty cycle discriminating circuit in which a period of a count clock signal is selected depending on a period of an input signal, that is, a count value of the input signal. Thereby, even if a period of the input signal varies over a wide range, it is possible to discriminate a duty cycle by using a constant re-load value.
However, with respect to the first prior art method, when a videotape is wound forward (fast-forward) or rewound in a video tape recorder (VTR), the period of the PBCTL signal varies depending on variations in motor speed. Even in such case, it is necessary to correctly discriminate the duty cycle of the PBCTL signal. In this case, in order to detect whether the PBCTL signal shows the VISS pattern or not, it is only necessary to discriminate the duty cycle between two kinds of duty cycles, that is, between 30% and 60%.
In the timing diagram of FIG. 11, the initial re-load value of the up/down counter 51 is 00H, that is, zero in hexadecimal notation. However, usually, when the duty cycle discrimination is to be performed, a middle value between the two kinds of duty cycles is previously stored in the preset value register 52, and the middle value stored in the preset value register 52 is re-loaded onto the signed up/down counter 51.
However, when a period of the PBCTL signal varies, the count value of the up/down counter 51 with sign bit after elapsing one period of the PBCTL signal also varies largely. Therefore, it is necessary to also change the value stored in the preset value register 52 according to the variation of the PBCTL signal.
If the value stored in the preset register 52 is not changed, it is impossible to correctly discriminate the duty cycle of the PBCTL signal. In order to change the value stored in the preset value register 52, it is necessary to produce the value to be stored in the preset value resistor 52, by using an external CPU and the like.
Also, the data to be stored in the preset register 52 is produced based on the expectation or anticipation of the period of the PBCTL signal to be inputted next time. Therefore, there is a possibility that an error of the data becomes large and it is difficult to determine when the data to be stored in the preset value register 52 is changed.
In the second prior art mentioned above, it is necessary to calculate the duty cycle every period of the signal to be discriminated, that is, the PBCTL signal, by the CPU. Therefore, when the period of the PBCTL signal becomes small, for example, 100 xcexcs, in a condition the video tape is wound forward (fast-forward) or rewound in a VTR, a processing load of the CPU becomes large. In the duty cycle discrimination of the VISS system, it is not necessary to obtain a precise duty cycle value, but it is only necessary to discriminate between the larger duty cycle and the smaller duty cycle. Therefore, it is a waste of CPU processing power to perform arithmetic operation for obtaining a duty cycle value every period of the PBCTL signal.
With respect to the third prior art method, since it is necessary to change a period of a count clock signal depending on a period of an input signal, that is, a PBCTL signal, a structure of the duty cycle discriminating circuit becomes complicated. Also, it is difficult to appropriately change the period of the count clock signal according to the up/down count period.
It is an object of the present invention to obviate the disadvantages of the conventional duty cycle discriminating circuits.
It is another object of the present invention to provide a duty cycle discriminating circuit in which a duty cycle of an input signal can be discriminated with a reduced error of discrimination.
It is still another object of the present invention to provide a duty cycle discriminating circuit in which a duty cycle of an input signal can be discriminated with a reduced error of discrimination and which has a simple circuit structure.
It is still another object of the present invention to provide a duty cycle discriminating circuit in which a duty cycle of an input signal can be discriminated with a reduced error of discrimination even when a period of the input signal varies greatly.
It is still another object of the present invention to provide a duty cycle discriminating circuit in which a duty cycle of an input signal can be discriminated without using an external CPU and the like for providing a discrimination threshold value and the like.
It is still another object of the present invention to provide a duty cycle discriminating circuit in which a duty cycle of an input signal can be discriminated without using an external CPU and the like for providing a discrimination threshold value and the like and with a reduced error of discrimination even when a period of the input signal varies greatly.
According to an aspect of the present invention, there is provided a duty cycle discriminating circuit comprising: an up/down counter with sign bit for counting up or counting down a count clock signal depending on a potential level of a signal to be discriminated; an up counter for counting up the count clock signal regardless of the potential level of the signal to be discriminated; an addend data generating circuit for producing an addend data having a value corresponding to a predetermined proportion of a count value of the up counter; and an addition circuit with sign bit for adding a count value of the up/down counter and the addend data produced by the addend data generating circuit, the sign bit of the addition circuit with sign bit is outputted as a discrimination result signal of the duty cycle discriminating circuit; wherein the predetermined proportion of the count value of the up counter is specified to perform duty cycle discrimination of the signal to be discriminated by using a desired threshold point of duty cycle discrimination.
In this case, it is preferable that the duty cycle discriminating circuit further comprises an edge detecting circuit which detects a leading edge of the signal to be discriminated and outputs a pulse like edge detection signal in response to the detection thereof.
It is also preferable that the duty cycle discriminating circuit further comprises a delay circuit which receives the edge detection signal and delays the edge detection signal for a predetermined time to output an initializing signal.
It is further preferable that the up/down counter is initialized by the initialization signal and the most significant bit (MSB) of the up/down counter is outputted as a sign bit.
It is advantageous that the addition circuit comprises an adder for adding the count value of the up/down counter and the addend data produced by the addend data generating circuit, and an addition result register for storing a result of addition of the adder, a sign bit of the addition result register being outputted as a discrimination result signal of the duty cycle discriminating circuit.
It is also advantageous that, in the addend data generating circuit, the count value from the up counter is right shifted by a predetermined number of bit or bits and xe2x80x9c0xe2x80x9d is inserted to each of corresponding number of upper bit or bits to obtain the addend data.
It is further advantageous that the count value from the up counter has 16 bits and is right shifted by 3 bits and wherein xe2x80x9c0xe2x80x9d is inserted to each of the upper 3 bits of the right shifted data to obtain 16 bits data as the addend data.
It is preferable that the addend data generating circuit comprises a plurality of registers storing count values from the up counter after right shifting the count value by different number of bits respectively, and a first selector for selectively outputting data stored in the registers depending on a shift number designating signal.
It is also preferable that the addend data generating circuit further comprises a complementary circuit which receives the data outputted from the first selector and generates a complementary data of the data outputted from the first selector, and a second selector for selectively outputting the data outputted from the first selector or the complementary data depending on a positive-negative designating signal.
It is further preferable that the addend data generating circuit further comprises a third selector for selectively outputting the data outputted from the second selector or the count value of the up down counter depending on a bypass designating signal.
It is advantageous that the duty cycle discriminating circuit comprises, in place of the addend data generating circuit, a multiplier circuit which receives the count value of the up counter, the edge detection signal and a multiplication constant designating signal, and which multiplies the count value of the up counter and a constant inputted as the multiplication constant designating signal in synchronization with an input of the edge detection signal to generate the addend data.
It is also advantageous that the duty cycle discriminating circuit further comprises a delay circuit which receives the edge detection signal and delays the edge detection signal for a predetermined time to output an initializing signal.
It is further advantageous that the addition circuit comprises an adder for adding the count value of the up/down counter and the addend data produced by the addend data generating circuit, and an addition result register for storing a result of addition of the adder, a sign bit of the addition result register being outputted as a discrimination result signal of the duty cycle discriminating circuit.
It is preferable that the addition circuit comprises an augend data register for storing the count value of the up/down counter as an augend data in response to a rising edge of the edge detection signal, an addend data register for storing the addend data in response to the rising edge of the edge detection signal, an adder for adding the data stored in the augend data register and the data stored in the addend data register, and an addition result register for storing a result of addition of the adder in response to a falling edge of the edge detection signal.
It is also preferable that the duty cycle discriminating circuit further comprises a delay circuit which receives the edge detection signal and delays the edge detection signal for a predetermined time to output an initializing signal.
It is further preferable that, in the addend data generating circuit, the count value from the up counter is right shifted by a predetermined number of bit or bits and xe2x80x9c0xe2x80x9d is inserted to each of corresponding number of upper bit or bits to obtain the addend data.
It is advantageous that the count value from the up counter has 16 bits and is right shifted by 3 bits and wherein xe2x80x9c0xe2x80x9d is inserted to each of the upper 3 bits of the right shifted data to obtain 16 bits data as the addend data.